? 2000 fairchild semiconductor corporation ds500127 www.fairchildsemi.com march 1998 revised december 2000 74vcx162839 low voltage 20-bit selectable register/buffer with 3.6v tolerant inputs/outputs and 26 ? series resistors in the outputs 74vcx162839 low voltage 20-bit selectable register/buffer with 3.6v tolerant inputs/outputs and 26 ? series resistors in the outputs general description the vcx162839 contains twenty non-inverting selectable buffered or registered paths. the device can be configured to operate in a registered, or flow through buffer mode by utilizing the register enable (rege) and clock (clk) sig- nals. the device operates in a 20-bit word wide mode. all outputs can be placed into 3-state through use of the oe pin. these devices are ideally suited for buffered or regis- tered 168 pin and 200 pin sdram dimm memory mod- ules. the 74vcx162839 is designed for low voltage (1.65v to 3.6v) v cc applications with i/o compatibility up to 3.6v. the 74vcx162839 is also designed with 26 ? series resis- tors in the outputs. this design reduces line noise in appli- cations such as memory address drivers, clock drivers, and bus transceivers/transmitters. the 74vcx162839 is fabricated with an advanced cmos technology to achieve high speed operation while maintain- ing low cmos power dissipation. features compatible with pc100 and pc133 dimm module specifications 1.65v?3.6v v cc supply operation 3.6v tolerant inputs and outputs 26 ? series resistors in the outputs t pd (clk to o n ) 4.1 ns max for 3.0v to 3.6v v cc 5.8 ns max for 2.3v to 2.7v v cc 9.8 ns max for 1.65v to 1.95v v cc power-off high impedance inputs and outputs supports live insertion and withdrawal (note 1) static drive (i oh /i ol ) 12 ma @ 3.0v v cc 8 ma @ 2.3v v cc 3 ma @ 1.65v v cc uses patented noise/emi reduction circuitry latch-up performance exceeds 300 ma esd performance: human body model > 2000v machine model > 200v note 1: to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ordering code: devices also available in tape and reel. specify by appending suffix letter ? x ? to the ordering code. logic symbol pin descriptions order number package number package description 74VCX162839MTD mtd56 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide pin names description oe output enable input (active low) i 0 ? i 19 inputs o 0 ? o 19 outputs clk clock input rege register enable input
www.fairchildsemi.com 2 74vcx162839 connection diagram truth table h = logic high l = logic low x = don ? t care, but not floating z = high impedance = low-to-high clock transition functional description the 74vcx162839 consists of twenty selectable non- inverting buffers or registers with word wide modes. mode functionality is selected through operation of the clk and rege pin as shown by the truth table. when rege is held at a logic high the device operates as a 20-bit register. data is transferred from i n to o n on the rising edge of the clk input. when the rege pin is held at a logic low the device operates in a flow through mode and data propa- gates directly from the i n to the o n outputs. all outputs can be 3-stated by holding the oe pin at a logic high. logic diagram inputs outputs clk rege i n oe o n hhl h hll l xlhlh xlll l xxxh z
3 www.fairchildsemi.com 74vcx162839 absolute maximum ratings (note 2) recommended operating conditions (note 4) note 2: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rat- ings. the ? recommended operating conditions ? table will define the condi- tions for actual device operation. note 3: i o absolute maximum rating must be observed. note 4: floating or unused inputs must be held high or low. dc electrical characteristics (2.7v < v cc 3.6v) note 5: outputs disabled or 3-state only. supply voltage (v cc ) ? 0.5v to + 4.6v dc input voltage (v i ) ? 0.5v to + 4.6v output voltage (v o ) outputs 3-state ? 0.5v to + 4.6v outputs active (note 3) ? 0.5v to v cc + 0.5v dc input diode current (i ik ) v i < 0v ? 50 ma dc output diode current (i ok ) v o < 0v ? 50 ma v o > v cc + 50 ma dc output source/sink current (i oh /i ol ) 50 ma dc v cc or gnd current per supply pin (i cc or gnd) 100 ma storage temperature range (t stg ) ? 65 c to + 150 c power supply operating 1.65v to 3.6v data retention only 1.2v to 3.6v input voltage ? 0.3v to + 3.6v output voltage (v o ) output in active states 0v to v cc output in ? off ? state 0v to 3.6v output current in i oh /i ol v cc = 3.0v to 3.6v 12 ma v cc = 2.3v to 2.7v 8 ma v cc = 1.65v to 2.3v 3 ma free air operating temperature (t a ) ? 40 c to + 85 c minimum input edge rate ( ? t/ ? v) v in = 0.8v to 2.0v, v cc = 3.0v 10 ns/v symbol parameter conditions v cc (v) min max units v ih high level input voltage 2.7 ? 3.6 2.0 v v il low level input voltage 2.7 ? 3.6 0.8 v v oh high level output voltage i oh = ? 100 a2.7 ? 3.6 v cc ? 0.2 v i oh = ? 6 ma 2.7 2.2 i oh = ? 8 ma 3.0 2.4 i oh = ? 12 ma 3.0 2.2 v ol low level output voltage i ol = 100 a2.7 ? 3.6 0.2 v i ol = 6 ma 2.7 0.4 i ol = 8 ma 3.0 0.55 i ol = 12 ma 3.0 0.8 i i input leakage current 0v v i 3.6v 2.7 ? 3.6 5.0 a i oz 3-state output leakage 0v v o 3.6v 2.7 ? 3.6 10 a v i = v ih or v il i off power-off leakage current 0v (v i , v o ) 3.6v 0 10 a i cc quiescent supply current v i = v cc or gnd 2.7 ? 3.6 20 a v cc (v i , v o ) 3.6v (note 5) 20 ? i cc increase in i cc per input v ih = v cc ? 0.6v 2.7 ? 3.6 750 a
www.fairchildsemi.com 4 74vcx162839 dc electrical characteristics (2.3v v cc 2.7v) note 6: outputs disabled or 3-state only. dc electrical characteristics (1.65v v cc < 2.3v) note 7: outputs disabled or 3-state only. symbol parameter conditions v cc (v) min max units v ih high level input voltage 2.3 ? 2.7 1.6 v v il low level input voltage 2.3 ? 2.7 0.7 v v oh high level output voltage i oh = ? 100 a2.3 ? 2.7 v cc ? 0.2 v i oh = ? 4 ma 2.3 2.0 i oh = ? 6 ma 2.3 1.8 i oh = ? 8 ma 2.3 1.7 v ol low level output voltage i ol = 100 a2.3 ? 2.7 0.2 v i ol = 6 ma 2.3 0.4 i ol = 8 ma 2.3 0.6 i i input leakage current 0v v i 3.6v 2.3 ? 2.7 5.0 a i oz 3-state output leakage 0v v o 3.6v 2.3 ? 2.7 10 a v i = v ih or v il i off power-off leakage current 0v (v i , v o ) 3.6v 0 10 a i cc quiescent supply current v i = v cc or gnd 2.3 ? 2.7 20 a v cc (v i , v o ) 3.6v (note 6) 20 symbol parameter conditions v cc (v) min max units v ih high level input voltage 1.65 - 2.3 0.65 x v cc v il low level input voltage 1.65 - 2.3 0.35 v cc v v oh high level output voltage i oh = ? 100 a1.65 - 2.3v cc ? 0.2 v i oh = ? 3 ma 1.65 1.25 v ol low level output voltage i ol = 100 a 1.65 - 2.3 0.2 v i ol = 3 ma 1.65 0.3 i i input leakage current 0v v i 3.6v 1.65 - 2.3 5.0 a i oz 3-state output leakage 0v v o 3.6v 1.65 - 2.3 10 a v i = v ih or v il i off power-off leakage current 0v (v i , v o ) 3.6v 0 10 a i cc quiescent supply current v i = v cc or gnd 1.65 - 2.3 20 a v cc (v i , v o ) 3.6v (note 7) 20
5 www.fairchildsemi.com 74vcx162839 ac electrical characteristics (note 8) note 8: for c l = 50 pf, add approximately 300 ps to the ac maximum specification. note 9: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). extended ac electrical characteristics (note 10) note 10: this parameter is guaranteed by characterization but not tested. dynamic switching characteristics capacitance symbol parameter t a = ? 40 c to + 85 c, c l = 30 pf, r l = 500 ? units v cc = 3.3v 0.3v v cc = 2.5v 0.2v v cc = 1.8v 0.15v min max min max min max f max maximum clock frequency 250 200 125 mhz t phl propagation delay i n to o n 0.8 3.5 1.0 4.9 1.5 9.8 ns t plh (rege = 0) t phl propagation delay clk to o n 0.8 4.1 1.0 5.8 1.5 9.8 ns t plh (rege = 1) t phl , t plh propagation delay rege to o n 0.8 4.9 1.0 6.4 1.5 9.8 ns t pzl , t pzh output enable time 0.8 4.3 1.0 6.1 1.5 9.8 ns t plz , t phz output disable time 0.8 4.3 1.0 4.9 1.5 8.8 ns t s setup time 1.0 1.0 2.5 ns t h hold time 0.7 0.7 1.0 ns t w pulse width 1.5 1.5 4.0 ns t oshl output to output skew 0.5 0.5 0.75 ns t oslh (note 9) symbol parameter t a = ? 0 c to + 85 c, r l = 500 ? v cc = 3.3v 0.3v units c l = 50 pf min max t phl , t plh propagation delay i n to o n (rege = 0) 1.0 3.8 ns t phl , t plh propagation delay clk to o n (rege = 1) 1.4 4.4 ns t phl , t plh propagation delay rege to o n 1.0 5.2 ns t pzl , t pzh output enable time 1.0 4.6 ns t plz , t phz output disable time 1.0 4.6 ns t s setup time 1.0 ns t h hold time 0.7 ns symbol parameter conditions v cc (v) t a = + 25 c units typical v olp quiet output dynamic peak v ol c l = 30 pf, v ih = v cc , v il = 0v 1.8 0.15 v 2.5 0.25 3.3 0.35 v olv quiet output dynamic valley v ol c l = 30 pf, v ih = v cc , v il = 0v 1.8 ? 0.15 v 2.5 ? 0.25 3.3 ? 0.35 v ohv quiet output dynamic valley v oh c l = 30 pf, v ih = v cc , v il = 0v 1.8 1.55 v 2.5 2.05 3.3 2.65 symbol parameter conditions t a = + 25 c units typical c in input capacitance v cc = 1.8v, 2.5v or 3.3v, v i = 0v or v cc 6pf c out output capacitance v i = 0v or v cc , v cc = 1.8v, 2.5v or 3.3v 7 pf c pd power dissipation capacitance v i = 0v or v cc , f = 10 mhz, 20 pf v cc = 1.8v, 2.5v or 3.3v
www.fairchildsemi.com 6 74vcx162839 ac loading and waveforms figure 1. ac test circuit figure 2. waveform for inverting and non-inverting functions figure 3. 3-state output high enable and disable times for low voltage logic figure 4. 3-state output low enable and disable times for low voltage logic figure 5. propagation delay, pulse width and t rec waveforms figure 6. setup time, hold time and recovery time for low voltage logic test switch t plh , t phl open t pzl , t plz 6v at v cc = 3.3 0.3v; v cc x 2 at v cc = 2.5 0.2v; 1.8v 0.15v t pzh , t phz gnd symbol v cc 3.3v 0.3v 2.5v 0.2v 1.8v 0.15v v mi 1.5v v cc /2 v cc /2 v mo 1.5v v cc /2 v cc /2 v x v ol + 0.3v v ol + 0.15v v ol + 0.15v v y v oh ? 0.3v v oh ? 0.15v v oh ? 0.15v
7 www.fairchildsemi.com 74vcx162839 low voltage 20-bit selectable register/buffer with 3.6v tolerant inputs/outputs and 26 ? series resistors in the outputs physical dimensions inches (millimeters) unless otherwise noted 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd56 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
|
